Triton · Gluon · MLIR

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34 examples
Triton / memory baselinetriton / hip:gfx950:64triton-vector-add-gfx950

add_kernel

The canonical masked vector add: a compact baseline for pointer, mask, and layout lowering.

Triton / reductiontriton / hip:gfx950:64triton-softmax-gfx950

softmax

Fused softmax on AMD: row reductions, numerical stabilization, and layout conversion.

Triton / reductiontriton / cuda:80:32triton-softmax-cuda80

softmax

The same fused softmax shape on CUDA, exposing target-specific lowering and LLVM passes.

Triton / randomnesstriton / hip:gfx950:64triton-dropout-gfx950

dropout_kernel

Seeded low-memory dropout with counter-based random values, masking, scaling, and stores.

Triton / normalizationtriton / hip:gfx950:64triton-layer-norm-gfx950

layer_norm_kernel

Layer normalization with mean/variance reductions and an affine epilogue.

Triton / tiled matmultriton / hip:gfx950:64triton-matmul-gfx950

matmul_kernel

Grouped, tiled matrix multiplication with dot lowering and AMD matrix-instruction paths.

Gluon / attentiongluon / hip:gfx950:64gluon-attention-gfx950

fused_attention

Fused attention lowering with scheduling, coalescing, and LLVM conversion.

Gluon / explicit layoutsgluon / hip:gfx950:64gluon-memcpy-layout-gfx950

memcpy_layout_kernel

A layout-declared memcpy that makes Gluon auto-encoding resolution visible.

Gluon / async memorygluon / cuda:80:32gluon-async-copy-cuda80

async_copy_kernel

Ampere Gluon async-copy pipeline: shared memory allocation, commit/wait, and lowering.

Liger / RMSNormtriton / hip:gfx950:64liger-rms-norm-gfx950

_rms_norm_forward_kernel

LinkedIn Liger production RMSNorm forward: Llama/Gemma casting modes, cached rstd, and affine epilogue.

Liger / SwiGLUtriton / hip:gfx950:64liger-swiglu-gfx950

_swiglu_forward_kernel

Liger fused SwiGLU MLP activation: SiLU(gate) * up with float32 sigmoid and gate multiplier.

Liger / Softmaxtriton / hip:gfx950:64liger-softmax-gfx950

_softmax_single_block_forward_kernel

Liger single-block row softmax: the production fast path when a row fits in one block.

Gluon / GFX950 GEMMgluon / hip:gfx950:64gluon-v9-beyond-hotloop-gfx950

v9_beyond_hotloop

AMD ROCm peak FP16 GEMM: XCD-aware PID remapping, async-copy MFMA pipeline, and AGPR allocation.

vLLM / SwiGLU-steptriton / hip:gfx950:64vllm-swiglustep-gfx950

_swiglustep_and_mul_kernel

vLLM GPT-OSS-style activation: clamped SiLU(gate) × up from a split gate/up row.

SGLang / softcaptriton / hip:gfx950:64sglang-softcap-gfx950

softcap_out_kernel

SGLang serving soft-cap: portable tanh-style softcap used on logits and attention scores.

ATOM / Gemma RMSNormtriton / hip:gfx950:64atom-gemma-rmsnorm-gfx950

_gemma_rmsnorm_kernel

AMD ATOM fused residual + Gemma RMSNorm with weight offset (1 + w) and persistent rows.

AITER / online softmaxtriton / hip:gfx950:64aiter-online-softmax-gfx950

_softmax_kernel_online

AMD AITER two-pass online softmax: streaming max/sum over wide rows for Instinct GPUs.

TensorRT-LLM / RMSNormtriton / cuda:80:32tensorrt-rms-norm-cuda80

rms_norm_kernel

NVIDIA TensorRT-LLM auto-deploy RMSNorm with constexpr stride/width and float32 weight multiply.

vLLM / attention mergetriton / cuda:80:32vllm-merge-attn-cuda80

merge_attn_states_kernel

vLLM split-KV attention merge: combines prefix/suffix partial outputs and LSE values.

vLLM / attention mergetriton / hip:gfx950:64vllm-merge-attn-gfx950

merge_attn_states_kernel

vLLM split-KV attention merge: combines prefix/suffix partial outputs and LSE values.

TensorRT-LLM / flash-decodetriton / cuda:80:32tensorrt-flash-decode-reduce-cuda80

_flash_decode_stage2_kernel

TensorRT-LLM flash-decode stage-2: reduces split-K partial attention outputs by LSE weights.

TensorRT-LLM / flash-decodetriton / hip:gfx950:64tensorrt-flash-decode-reduce-gfx950

_flash_decode_stage2_kernel

TensorRT-LLM flash-decode stage-2: reduces split-K partial attention outputs by LSE weights.

TensorRT-LLM / MoE routingtriton / cuda:80:32tensorrt-moe-routing-cuda80

_fused_topk_softmax_kernel

TensorRT-LLM fused MoE top-k + softmax: selects experts from raw logits then softmaxes only k.

TensorRT-LLM / MoE routingtriton / hip:gfx950:64tensorrt-moe-routing-gfx950

_fused_topk_softmax_kernel

TensorRT-LLM fused MoE top-k + softmax: selects experts from raw logits then softmaxes only k.

AITER / MoE aligntriton / cuda:80:32aiter-moe-align-cuda80

_moe_align_block_size_stage1_kernel

AMD AITER MoE align stage-1: counts tokens per expert before block padding for fused MoE GEMMs.

AITER / MoE aligntriton / hip:gfx950:64aiter-moe-align-gfx950

_moe_align_block_size_stage1_kernel

AMD AITER MoE align stage-1: counts tokens per expert before block padding for fused MoE GEMMs.

vLLM / MoE combinetriton / cuda:80:32vllm-moe-mul-sum-cuda80

moe_fused_mul_sum_kernel

vLLM MoE fused mul+sum: weights expert outputs by router scores and reduces across top-k.

vLLM / MoE combinetriton / hip:gfx950:64vllm-moe-mul-sum-gfx950

moe_fused_mul_sum_kernel

vLLM MoE fused mul+sum: weights expert outputs by router scores and reduces across top-k.

vLLM / MoE fused GEMMtriton / cuda:80:32vllm-fused-moe-cuda80

fused_moe_kernel

vLLM fused MoE expert GEMM: grouped token×expert matmul over sorted/padded token ids.

vLLM / MoE fused GEMMtriton / hip:gfx950:64vllm-fused-moe-gfx950

fused_moe_kernel

vLLM fused MoE expert GEMM: grouped token×expert matmul over sorted/padded token ids.

SGLang / MoE routertriton / cuda:80:32sglang-moe-router-cuda80

_router_triton_kernel

SGLang MoE fused gate: sigmoid scoring, biased top-k selection, and optional shared experts.

SGLang / MoE routertriton / hip:gfx950:64sglang-moe-router-gfx950

_router_triton_kernel

SGLang MoE fused gate: sigmoid scoring, biased top-k selection, and optional shared experts.

Liger / MoE histogramtriton / cuda:80:32liger-moe-histogram-cuda80

_moe_router_histogram_kernel

Liger SonicMoE-style router histogram: counts (token, k) assignments per expert per tile.

Liger / MoE histogramtriton / hip:gfx950:64liger-moe-histogram-gfx950

_moe_router_histogram_kernel

Liger SonicMoE-style router histogram: counts (token, k) assignments per expert per tile.

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